 
cpldfit:  version I.33                              Xilinx Inc.
                                  Fitter Report
Design Name: main                                Date:  5-19-2008,  2:00PM
Device Used: XC9536-10-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
34 /36  ( 94%) 131 /180  ( 73%) 42 /72  ( 58%)   15 /36  ( 42%) 27 /34  ( 79%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          18/18*      26/36       26          45/90       6/17
FB2          16/18       16/36       16          86/90       9/17
             -----       -----                   -----       -----     
             34/36       42/72                  131/180     15/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   11          11    |  I/O              :    26      28
Output        :   14          14    |  GCK/IO           :     1       3
Bidirectional :    1           1    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 34 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB1,
   because too many function block product terms are required. Buffering output
   signal D1S0 to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB1,
   because too many function block product terms are required. Buffering output
   signal B1S0 to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
   because too many function block product terms are required. Buffering output
   signal D2S0 to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
   because too many function block product terms are required. Buffering output
   signal G2S0 to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
   because too many function block product terms are required. Buffering output
   signal G1S0 to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 15 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
COM0                1     1     FB1_12  14   I/O     I/O     STD  FAST SET
A1S0                8     5     FB1_13  18   I/O     O       STD  FAST 
B1S0                1     1     FB1_14  19   I/O     O       STD  FAST 
C1S0                6     5     FB1_15  20   I/O     O       STD  FAST 
D1S0                1     1     FB1_16  22   I/O     O       STD  FAST 
E1S0                5     5     FB1_17  24   I/O     O       STD  FAST 
G2S0                1     1     FB2_9   36   I/O     O       STD  FAST 
F2S0                5     5     FB2_10  35   I/O     O       STD  FAST 
E2S0                5     5     FB2_11  34   I/O     O       STD  FAST 
D2S0                1     1     FB2_12  33   I/O     O       STD  FAST 
C2S0                6     5     FB2_13  29   I/O     O       STD  FAST 
B2S0                8     5     FB2_14  28   I/O     O       STD  FAST 
A2S0                8     5     FB2_15  27   I/O     O       STD  FAST 
G1S0                1     1     FB2_16  26   I/O     O       STD  FAST 
F1S0                5     5     FB2_17  25   I/O     O       STD  FAST 

** 19 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
n_n76               1     4     FB1_1   STD  RESET
n_n87               2     4     FB1_2   STD  RESET
n_n86               2     4     FB1_3   STD  RESET
n_n85               2     4     FB1_4   STD  RESET
n_n84               2     4     FB1_5   STD  RESET
n_n82               2     4     FB1_6   STD  RESET
n_n81               2     4     FB1_7   STD  RESET
n_n77               2     4     FB1_8   STD  RESET
n_n74               2     6     FB1_9   STD  RESET
n_n73               2     5     FB1_10  STD  RESET
n_n72               2     4     FB1_11  STD  RESET
n_n71               2     3     FB1_18  STD  RESET
G1S0_BUFR           8     5     FB2_2   STD  
n_n80               2     4     FB2_3   STD  RESET
n_n79               2     4     FB2_4   STD  RESET
G2S0_BUFR           8     5     FB2_5   STD  
B1S0_BUFR           8     5     FB2_7   STD  
D2S0_BUFR           9     5     FB2_8   STD  
D1S0_BUFR           9     5     FB2_18  STD  

** 12 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
BDATA0              FB1_1   2    I/O     I
ADATA0              FB1_2   3    I/O     I
clk                 FB1_3   5    GCK/I/O GCK
ADATA1              FB1_4   4    I/O     I
ADATA2              FB1_6   8    I/O     I
ADATA3              FB1_8   9    I/O     I
BDATA1              FB1_9   11   I/O     I
BDATA2              FB1_10  12   I/O     I
BDATA3              FB1_11  13   I/O     I
ACK0                FB2_1   1    I/O     I
CLKIN0              FB2_2   44   I/O     I
RESET0              FB2_4   43   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               26/10
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
n_n76                 1       0     0   4     FB1_1   2     I/O     I
n_n87                 2       0     0   3     FB1_2   3     I/O     I
n_n86                 2       0     0   3     FB1_3   5     GCK/I/O GCK
n_n85                 2       0     0   3     FB1_4   4     I/O     I
n_n84                 2       0     0   3     FB1_5   6     GCK/I/O (b)
n_n82                 2       0     0   3     FB1_6   8     I/O     I
n_n81                 2       0     0   3     FB1_7   7     GCK/I/O (b)
n_n77                 2       0     0   3     FB1_8   9     I/O     I
n_n74                 2       0     0   3     FB1_9   11    I/O     I
n_n73                 2       0     0   3     FB1_10  12    I/O     I
n_n72                 2       0     0   3     FB1_11  13    I/O     I
COM0                  1       0   \/2   2     FB1_12  14    I/O     I/O
A1S0                  8       3<-   0   0     FB1_13  18    I/O     O
B1S0                  1       0   /\1   3     FB1_14  19    I/O     O
C1S0                  6       1<-   0   0     FB1_15  20    I/O     O
D1S0                  1       0   /\1   3     FB1_16  22    I/O     O
E1S0                  5       0     0   0     FB1_17  24    I/O     O
n_n71                 2       0     0   3     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ACK0              10: COM0.PIN          19: n_n79 
  2: ADATA2            11: D1S0_BUFR         20: n_n80 
  3: ADATA3            12: RESET0            21: n_n81 
  4: B1S0_BUFR         13: n_n71             22: n_n82 
  5: BDATA0            14: n_n72             23: n_n84 
  6: BDATA1            15: n_n73             24: n_n85 
  7: BDATA2            16: n_n74             25: n_n86 
  8: BDATA3            17: n_n76             26: n_n87 
  9: CLKIN0            18: n_n77            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
n_n76                ........X..X....XX...................... 4       4
n_n87                X......X...X.............X.............. 4       4
n_n86                X.....X....X............X............... 4       4
n_n85                X....X.....X...........X................ 4       4
n_n84                X...X......X..........X................. 4       4
n_n82                X.X........X.........X.................. 4       4
n_n81                XX.........X........X................... 4       4
n_n77                ........X..X....XX...................... 4       4
n_n74                ...........XXXXXX....................... 6       6
n_n73                ...........XXXX.X....................... 5       5
n_n72                ...........XXX..X....................... 4       4
COM0                 ...............X........................ 1       1
A1S0                 .........X........XXXX.................. 5       5
B1S0                 ...X.................................... 1       1
C1S0                 .........X........XXXX.................. 5       5
D1S0                 ..........X............................. 1       1
E1S0                 .........X........XXXX.................. 5       5
n_n71                ...........XX...X....................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               16/20
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\4   1     FB2_1   1     I/O     I
G1S0_BUFR             8       3<-   0   0     FB2_2   44    I/O     I
n_n80                 2       0   /\3   0     FB2_3   42    GTS/I/O (b)
n_n79                 2       0   \/3   0     FB2_4   43    I/O     I
G2S0_BUFR             8       3<-   0   0     FB2_5   40    GTS/I/O (b)
(unused)              0       0   \/3   2     FB2_6   39    GSR/I/O (b)
B1S0_BUFR             8       3<-   0   0     FB2_7   38    I/O     (b)
D2S0_BUFR             9       4<-   0   0     FB2_8   37    I/O     (b)
G2S0                  1       0   /\4   0     FB2_9   36    I/O     O
F2S0                  5       0     0   0     FB2_10  35    I/O     O
E2S0                  5       0     0   0     FB2_11  34    I/O     O
D2S0                  1       0   \/3   1     FB2_12  33    I/O     O
C2S0                  6       3<- \/2   0     FB2_13  29    I/O     O
B2S0                  8       3<-   0   0     FB2_14  28    I/O     O
A2S0                  8       4<- /\1   0     FB2_15  27    I/O     O
G1S0                  1       0   /\4   0     FB2_16  26    I/O     O
F1S0                  5       0     0   0     FB2_17  25    I/O     O
D1S0_BUFR             9       4<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ACK0               7: G2S0_BUFR         12: n_n82 
  2: ADATA0             8: RESET0            13: n_n84 
  3: ADATA1             9: n_n79             14: n_n85 
  4: COM0.PIN          10: n_n80             15: n_n86 
  5: D2S0_BUFR         11: n_n81             16: n_n87 
  6: G1S0_BUFR        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
G1S0_BUFR            ...X....XXXX............................ 5       5
n_n80                X.X....X.X.............................. 4       4
n_n79                XX.....XX............................... 4       4
G2S0_BUFR            ...X........XXXX........................ 5       5
B1S0_BUFR            ...X....XXXX............................ 5       5
D2S0_BUFR            ...X........XXXX........................ 5       5
G2S0                 ......X................................. 1       1
F2S0                 ...X........XXXX........................ 5       5
E2S0                 ...X........XXXX........................ 5       5
D2S0                 ....X................................... 1       1
C2S0                 ...X........XXXX........................ 5       5
B2S0                 ...X........XXXX........................ 5       5
A2S0                 ...X........XXXX........................ 5       5
G1S0                 .....X.................................. 1       1
F1S0                 ...X....XXXX............................ 5       5
D1S0_BUFR            ...X....XXXX............................ 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


A1S0 <= ((COM0_OBUF.EXP)
	OR (_5_.EXP)
	OR (n_n80 AND n_n82 AND COM0.PIN)
	OR (n_n80 AND NOT n_n82 AND NOT COM0.PIN)
	OR (n_n81 AND n_n82 AND COM0.PIN)
	OR (NOT n_n80 AND n_n81 AND NOT n_n79 AND COM0.PIN)
	OR (n_n81 AND n_n79 AND NOT n_n82 AND NOT COM0.PIN));


A2S0 <= ((_8_.EXP)
	OR (n_n85 AND n_n87 AND COM0.PIN)
	OR (n_n85 AND NOT n_n87 AND NOT COM0.PIN)
	OR (n_n86 AND n_n87 AND COM0.PIN)
	OR (NOT n_n85 AND n_n86 AND NOT n_n84 AND COM0.PIN));


B1S0 <= B1S0_BUFR;


B1S0_BUFR <= ((EXP1_.EXP)
	OR (n_n80 AND n_n82 AND COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND NOT COM0.PIN)
	OR (n_n81 AND n_n82 AND COM0.PIN)
	OR (NOT n_n81 AND NOT n_n82 AND NOT COM0.PIN)
	OR (NOT n_n80 AND n_n81 AND n_n79 AND COM0.PIN));


B2S0 <= ((C2S0_OBUF.EXP)
	OR (A2S0_OBUF.EXP)
	OR (n_n85 AND n_n87 AND COM0.PIN)
	OR (NOT n_n85 AND NOT n_n86 AND NOT COM0.PIN)
	OR (n_n86 AND n_n87 AND COM0.PIN)
	OR (NOT n_n86 AND NOT n_n87 AND NOT COM0.PIN)
	OR (NOT n_n85 AND n_n86 AND n_n84 AND COM0.PIN));


C1S0 <= ((_4_.EXP)
	OR (n_n80 AND n_n82 AND COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND NOT COM0.PIN)
	OR (n_n81 AND n_n82 AND COM0.PIN)
	OR (n_n81 AND NOT n_n82 AND NOT COM0.PIN)
	OR (n_n79 AND NOT n_n82 AND NOT COM0.PIN));


C2S0 <= ((_6_.EXP)
	OR (n_n85 AND n_n87 AND COM0.PIN)
	OR (n_n86 AND n_n87 AND COM0.PIN)
	OR (n_n84 AND NOT n_n87 AND NOT COM0.PIN));

FDCPE_COM0: FDCPE port map (COM0,NOT n_n74,clk,'0','0');


D1S0 <= D1S0_BUFR;


D1S0_BUFR <= NOT (((EXP0_.EXP)
	OR (n_n80 AND n_n82 AND NOT COM0.PIN)
	OR (n_n79 AND n_n82 AND NOT COM0.PIN)
	OR (n_n80 AND NOT n_n81 AND NOT n_n82 AND COM0.PIN)
	OR (n_n80 AND NOT n_n79 AND NOT n_n82 AND COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND NOT n_n79 AND COM0.PIN)));


D2S0 <= D2S0_BUFR;


D2S0_BUFR <= NOT (((_7_.EXP)
	OR (n_n85 AND n_n87 AND NOT COM0.PIN)
	OR (n_n84 AND n_n87 AND NOT COM0.PIN)
	OR (n_n85 AND NOT n_n86 AND NOT n_n87 AND COM0.PIN)
	OR (n_n85 AND NOT n_n84 AND NOT n_n87 AND COM0.PIN)
	OR (NOT n_n85 AND NOT n_n86 AND NOT n_n84 AND COM0.PIN)));


E1S0 <= NOT (((n_n79 AND NOT COM0.PIN)
	OR (n_n80 AND n_n82 AND NOT COM0.PIN)
	OR (NOT n_n80 AND n_n81 AND NOT COM0.PIN)
	OR (n_n80 AND NOT n_n79 AND NOT n_n82 AND COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND NOT n_n79 AND COM0.PIN)));


E2S0 <= NOT (((n_n84 AND NOT COM0.PIN)
	OR (n_n85 AND n_n87 AND NOT COM0.PIN)
	OR (NOT n_n85 AND n_n86 AND NOT COM0.PIN)
	OR (n_n85 AND NOT n_n84 AND NOT n_n87 AND COM0.PIN)
	OR (NOT n_n85 AND NOT n_n86 AND NOT n_n84 AND COM0.PIN)));






F1S0 <= NOT (COM0.PIN
	 XOR 
F1S0 <= NOT (((n_n80 AND NOT n_n81)
	OR (n_n80 AND n_n79)
	OR (n_n81 AND n_n82)
	OR (NOT n_n81 AND n_n79 AND NOT n_n82)));


F2S0 <= NOT (COM0.PIN
	 XOR 
F2S0 <= NOT (((n_n85 AND NOT n_n86)
	OR (n_n85 AND n_n84)
	OR (n_n86 AND n_n87)
	OR (NOT n_n86 AND n_n84 AND NOT n_n87)));


G1S0 <= G1S0_BUFR;


G1S0_BUFR <= ((n_n80.EXP)
	OR (n_n80 AND n_n82 AND COM0.PIN)
	OR (n_n81 AND n_n82 AND COM0.PIN)
	OR (n_n80 AND n_n81 AND n_n79 AND COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND n_n82 AND NOT COM0.PIN)
	OR (NOT n_n80 AND NOT n_n81 AND NOT n_n82 AND COM0.PIN));


G2S0 <= G2S0_BUFR;


G2S0_BUFR <= ((n_n79.EXP)
	OR (n_n85 AND n_n87 AND COM0.PIN)
	OR (n_n86 AND n_n87 AND COM0.PIN)
	OR (n_n85 AND n_n86 AND n_n84 AND COM0.PIN)
	OR (NOT n_n85 AND NOT n_n86 AND n_n87 AND NOT COM0.PIN)
	OR (NOT n_n85 AND NOT n_n86 AND NOT n_n87 AND COM0.PIN));

FDCPE_n_n71: FDCPE port map (n_n71,n_n71_D,clk,'0','0');
n_n71_D <= ((NOT RESET0 AND n_n76 AND NOT n_n71)
	OR (NOT RESET0 AND NOT n_n76 AND n_n71));

FTCPE_n_n72: FTCPE port map (n_n72,n_n72_T,clk,'0','0');
n_n72_T <= ((RESET0 AND n_n72)
	OR (NOT RESET0 AND n_n76 AND n_n71));

FTCPE_n_n73: FTCPE port map (n_n73,n_n73_T,clk,'0','0');
n_n73_T <= ((RESET0 AND n_n73)
	OR (NOT RESET0 AND n_n76 AND n_n71 AND n_n72));

FTCPE_n_n74: FTCPE port map (n_n74,n_n74_T,clk,'0','0');
n_n74_T <= ((RESET0 AND n_n74)
	OR (NOT RESET0 AND n_n76 AND n_n71 AND n_n72 AND n_n73));

FDCPE_n_n76: FDCPE port map (n_n76,n_n76_D,clk,'0','0');
n_n76_D <= (NOT RESET0 AND CLKIN0 AND NOT n_n76 AND NOT n_n77);

FDCPE_n_n77: FDCPE port map (n_n77,n_n77_D,clk,'0','0');
n_n77_D <= ((NOT RESET0 AND n_n76 AND NOT n_n77)
	OR (NOT RESET0 AND CLKIN0 AND NOT n_n76 AND n_n77));

FDCPE_n_n79: FDCPE port map (n_n79,n_n79_D,clk,'0','0');
n_n79_D <= ((NOT RESET0 AND n_n79 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND ADATA0));

FDCPE_n_n80: FDCPE port map (n_n80,n_n80_D,clk,'0','0');
n_n80_D <= ((NOT RESET0 AND n_n80 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND ADATA1));

FDCPE_n_n81: FDCPE port map (n_n81,n_n81_D,clk,'0','0');
n_n81_D <= ((NOT RESET0 AND n_n81 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND ADATA2));

FDCPE_n_n82: FDCPE port map (n_n82,n_n82_D,clk,'0','0');
n_n82_D <= ((NOT RESET0 AND n_n82 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND ADATA3));

FDCPE_n_n84: FDCPE port map (n_n84,n_n84_D,clk,'0','0');
n_n84_D <= ((NOT RESET0 AND n_n84 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND BDATA0));

FDCPE_n_n85: FDCPE port map (n_n85,n_n85_D,clk,'0','0');
n_n85_D <= ((NOT RESET0 AND n_n85 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND BDATA1));

FDCPE_n_n86: FDCPE port map (n_n86,n_n86_D,clk,'0','0');
n_n86_D <= ((NOT RESET0 AND n_n86 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND BDATA2));

FDCPE_n_n87: FDCPE port map (n_n87,n_n87_D,clk,'0','0');
n_n87_D <= ((NOT RESET0 AND n_n87 AND ACK0)
	OR (NOT RESET0 AND NOT ACK0 AND BDATA3));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9536-10-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ACK0                             23 GND                           
  2 BDATA0                           24 E1S0                          
  3 ADATA0                           25 F1S0                          
  4 ADATA1                           26 G1S0                          
  5 clk                              27 A2S0                          
  6 TIE                              28 B2S0                          
  7 TIE                              29 C2S0                          
  8 ADATA2                           30 TDO                           
  9 ADATA3                           31 GND                           
 10 GND                              32 VCC                           
 11 BDATA1                           33 D2S0                          
 12 BDATA2                           34 E2S0                          
 13 BDATA3                           35 F2S0                          
 14 COM0                             36 G2S0                          
 15 TDI                              37 TIE                           
 16 TMS                              38 TIE                           
 17 TCK                              39 TIE                           
 18 A1S0                             40 TIE                           
 19 B1S0                             41 VCC                           
 20 C1S0                             42 TIE                           
 21 VCC                              43 RESET0                        
 22 D1S0                             44 CLKIN0                        


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25
