 
cpldfit:  version I.33                              Xilinx Inc.
                                  Fitter Report
Design Name: main                                Date:  5-19-2008,  1:41PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
103/108 ( 95%) 399 /540  ( 74%) 198/216 ( 92%)   80 /108 ( 74%) 24 /69  ( 35%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          15/18       36/36*      38          75/90       6/12
FB2          18/18*      36/36*      36          78/90       0/12
FB3          17/18       36/36*      36          83/90       7/12
FB4          17/18       36/36*      36          58/90       0/11
FB5          18/18*      31/36       31          63/90       0/11
FB6          18/18*      23/36       23          42/90       0/11
             -----       -----                   -----       -----     
            103/108     198/216                 399/540     13/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   10          10    |  I/O              :    23      63
Output        :   13          13    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     24          24

** Power Data **

There are 103 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 13 Outputs **

Signal               Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                 Pts   Inps          No.  Type    Use     Mode Rate State
ACK0                 1     5     FB1_6   4    I/O     O       STD  FAST SET
BCD0P0               7     8     FB1_8   5    I/O     O       STD  FAST RESET
BCD0P1               7     9     FB1_9   6    I/O     O       STD  FAST RESET
BCD0P2               19    12    FB1_11  7    I/O     O       STD  FAST RESET
BCD0P3               7     8     FB1_15  11   I/O     O       STD  FAST RESET
BCD1P0               2     5     FB1_17  13   I/O     O       STD  FAST RESET
BCD1P1               5     8     FB3_2   14   I/O     O       STD  FAST RESET
BCD1P2               9     10    FB3_3   15   I/O     O       STD  FAST RESET
BCD1P3               3     6     FB3_5   17   I/O     O       STD  FAST RESET
BCD2P0               2     5     FB3_6   18   I/O     O       STD  FAST RESET
BCD2P1               2     5     FB3_8   19   I/O     O       STD  FAST RESET
BCD2P2               5     10    FB3_9   20   I/O     O       STD  FAST RESET
BCD2P3               3     6     FB3_11  21   I/O     O       STD  FAST RESET

** 90 Buried Nodes **

Signal               Total Total Loc     Pwr  Reg Init
Name                 Pts   Inps          Mode State
n_n444               3     5     FB1_1   STD  RESET
n_n528               2     4     FB1_2   STD  RESET
n_n527               2     4     FB1_3   STD  RESET
n_n159               2     5     FB1_4   STD  RESET
n_n612/n_n612_D2     3     7     FB1_5   STD  
$OpTx$FX_DC$299      3     5     FB1_13  STD  
n_n123               4     7     FB1_14  STD  RESET
n_n445               6     7     FB1_16  STD  RESET
n_n487/n_n487_D2     7     9     FB1_18  STD  
N14/N14_D2           12    10    FB2_1   STD  
n_n567/n_n567_D2     2     7     FB2_2   STD  
n_n544               2     6     FB2_3   STD  RESET
n_n541               2     6     FB2_4   STD  RESET
$OpTx$FX_DC$281      2     6     FB2_5   STD  
n_n542               3     6     FB2_6   STD  RESET
n_n525               3     5     FB2_7   STD  RESET
n_n543               4     6     FB2_8   STD  RESET
n_n526               4     6     FB2_9   STD  RESET
N16/N16_D2           4     9     FB2_10  STD  
N12/N12_D2           4     9     FB2_11  STD  
n_n512               5     8     FB2_12  STD  RESET
n_n511               5     8     FB2_13  STD  RESET
n_n510               5     8     FB2_14  STD  RESET
n_n446               8     10    FB2_15  STD  RESET
n_n585               3     5     FB2_16  STD  RESET
N18/N18_D2           8     11    FB2_17  STD  
n_n584               2     4     FB2_18  STD  RESET
n_n509               1     7     FB3_1   STD  RESET
n_n349/n_n349_D216_  3     8     FB3_4   STD  
n_n273               12    13    FB3_7   STD  RESET
n_n272               10    12    FB3_10  STD  RESET
n_n288               2     6     FB3_13  STD  RESET
n_n396/n_n396_D2     2     4     FB3_14  STD  
n_n271               8     11    FB3_15  STD  RESET
n_n503               2     4     FB3_16  STD  RESET
n_n274               13    13    FB3_17  STD  RESET
n_n125               1     1     FB3_18  STD  RESET
n_n126               1     1     FB4_2   STD  RESET
n_n275               2     6     FB4_3   STD  RESET
n_n268               2     6     FB4_4   STD  RESET

Signal               Total Total Loc     Pwr  Reg Init
Name                 Pts   Inps          Mode State
n_n267               2     6     FB4_5   STD  RESET
n_n712/n_n712_D2     3     4     FB4_6   STD  
n_n282               3     7     FB4_7   STD  RESET
n_n281               3     7     FB4_8   STD  RESET
n_n280               3     7     FB4_9   STD  RESET
n_n279               3     7     FB4_10  STD  RESET
n_n278               3     7     FB4_11  STD  RESET
n_n277               3     7     FB4_12  STD  RESET
n_n276               3     7     FB4_13  STD  RESET
$OpTx$FX_DC$297      4     7     FB4_14  STD  
n_n269               5     9     FB4_15  STD  RESET
N183/N183_D2         5     11    FB4_16  STD  
n_n270               6     10    FB4_17  STD  RESET
N96/N96_D2           7     7     FB4_18  STD  
n_n428               1     7     FB5_1   STD  RESET
N193/N193_D2         1     10    FB5_2   STD  
n_n463               2     6     FB5_3   STD  RESET
n_n460               2     6     FB5_4   STD  RESET
$OpTx$FX_DC$314      2     6     FB5_5   STD  
n_n586               3     6     FB5_6   STD  RESET
n_n583               3     6     FB5_7   STD  RESET
n_n505               3     6     FB5_8   STD  RESET
n_n504               3     5     FB5_9   STD  RESET
n_n502               3     6     FB5_10  STD  RESET
n_n461               3     6     FB5_11  STD  RESET
n_n462               4     6     FB5_12  STD  RESET
$OpTx$FX_DC$289      4     5     FB5_13  STD  
n_n431               5     8     FB5_14  STD  RESET
n_n430               5     8     FB5_15  STD  RESET
n_n429               5     8     FB5_16  STD  RESET
n_n447               6     10    FB5_17  STD  RESET
N98/N98_D2           8     6     FB5_18  STD  
N5/N5_D2             1     7     FB6_1   STD  
N4/N4_D2             1     7     FB6_2   STD  
n_n340               2     4     FB6_3   STD  RESET
n_n290               2     6     FB6_4   STD  RESET
n_n289               2     6     FB6_5   STD  RESET
n_n287               2     6     FB6_6   STD  RESET
n_n286               2     6     FB6_7   STD  RESET
n_n283               2     4     FB6_8   STD  RESET

Signal               Total Total Loc     Pwr  Reg Init
Name                 Pts   Inps          Mode State
n_n150               2     3     FB6_9   STD  RESET
n_n149               2     6     FB6_10  STD  RESET
N169/N169_D2         2     6     FB6_11  STD  
n_n342               3     6     FB6_12  STD  RESET
n_n341               3     5     FB6_13  STD  RESET
n_n339               3     6     FB6_14  STD  RESET
n_n311/n_n311_D2     3     6     FB6_15  STD  
n_n285               3     6     FB6_16  STD  RESET
n_n284               3     5     FB6_17  STD  RESET
n_n122               4     10    FB6_18  STD  RESET

** 11 Inputs **

Signal               Loc     Pin  Pin     Pin     
Name                         No.  Type    Use     
ADDATA5              FB1_2   1    I/O     I
ADDATA6              FB1_3   2    I/O     I
ADDATA7              FB1_5   3    I/O     I
clk                  FB1_12  9    GCK/I/O GCK
RESET0               FB2_6   75   I/O     I
REQ0                 FB2_11  79   I/O     I
ADDATA0              FB2_12  80   I/O     I
ADDATA1              FB2_14  81   I/O     I
ADDATA2              FB2_15  82   I/O     I
ADDATA3              FB2_16  83   I/O     I
ADDATA4              FB2_17  84   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  38
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
n_n444                3       0   /\2   0     FB1_1         (b)     (b)
n_n528                2       0     0   3     FB1_2   1     I/O     I
n_n527                2       0     0   3     FB1_3   2     I/O     I
n_n159                2       0     0   3     FB1_4         (b)     (b)
n_n612/n_n612_D2      3       0     0   2     FB1_5   3     I/O     I
ACK0                  1       0   \/1   3     FB1_6   4     I/O     O
(unused)              0       0   \/5   0     FB1_7         (b)     (b)
BCD0P0                7       6<- \/4   0     FB1_8   5     I/O     O
BCD0P1                7       4<- \/2   0     FB1_9   6     I/O     O
(unused)              0       0   \/5   0     FB1_10        (b)     (b)
BCD0P2               19      14<-   0   0     FB1_11  7     I/O     O
(unused)              0       0   /\5   0     FB1_12  9     GCK/I/O GCK
$OpTx$FX_DC$299       3       0   /\2   0     FB1_13        (b)     (b)
n_n123                4       0   \/1   0     FB1_14  10    GCK/I/O (b)
BCD0P3                7       2<-   0   0     FB1_15  11    I/O     O
n_n445                6       2<- /\1   0     FB1_16  12    GCK/I/O (b)
BCD1P0                2       0   /\2   1     FB1_17  13    I/O     O
n_n487/n_n487_D2      7       2<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$289   14: N14/N14_D2        27: n_n287 
  2: $OpTx$FX_DC$314   15: N16/N16_D2        28: n_n349/n_n349_D216_ 
  3: ACK0              16: N18/N18_D2        29: n_n396/n_n396_D2 
  4: ADDATA0           17: N193/N193_D2      30: n_n428 
  5: ADDATA3           18: N5/N5_D2          31: n_n429 
  6: BCD0P0            19: N96/N96_D2        32: n_n430 
  7: BCD0P1            20: N98/N98_D2        33: n_n444 
  8: BCD0P2            21: RESET0            34: n_n445 
  9: BCD0P3            22: n_n122            35: n_n446 
 10: BCD1P0            23: n_n123            36: n_n525 
 11: BCD2P0            24: n_n149            37: n_n527 
 12: BCD2P2            25: n_n150            38: n_n528 
 13: FC_0_.OUT         26: n_n159           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
n_n444               .X...................XX......X..X....... 5       5
n_n528               ...............X.....XX..............X.. 4       4
n_n527               ..............X......XX.............X... 4       4
n_n159               ..X.................XXX..X.............. 5       5
n_n612/n_n612_D2     ...X..............X..XX.........XX.X.... 7       7
ACK0                 ..X.................XXX..X.............. 5       5
BCD0P0               ...X.X..........X...XXX.........X..X.... 8       8
BCD0P1               ...X..X.........X.X.XXX.........X..X.... 9       9
BCD0P2               ...X...X........X.X.XXX.....X...XXXX.... 12      12
$OpTx$FX_DC$299      ..........XX.........XX....X............ 5       5
n_n123               X...........X....X..X.X@@............... 7       5
BCD0P3               ....X...X....X..X..XXXX................. 8       8
n_n445               .X...................XX......XX.XX...... 7       7
BCD1P0               X........X.......X..X.....X............. 5       5
n_n487/n_n487_D2     .X...................XX......XXXXXX..... 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
N14/N14_D2           12       7<-   0   0     FB2_1         (b)     (b)
n_n567/n_n567_D2      2       1<- /\4   0     FB2_2   71    I/O     (b)
n_n544                2       0   /\1   2     FB2_3   72    I/O     (b)
n_n541                2       0     0   3     FB2_4         (b)     (b)
$OpTx$FX_DC$281       2       0     0   3     FB2_5   74    GSR/I/O (b)
n_n542                3       0     0   2     FB2_6   75    I/O     I
n_n525                3       0     0   2     FB2_7         (b)     (b)
n_n543                4       0   \/1   0     FB2_8   76    GTS/I/O (b)
n_n526                4       1<- \/2   0     FB2_9   77    GTS/I/O (b)
N16/N16_D2            4       2<- \/3   0     FB2_10        (b)     (b)
N12/N12_D2            4       3<- \/4   0     FB2_11  79    I/O     I
n_n512                5       4<- \/4   0     FB2_12  80    I/O     I
n_n511                5       4<- \/4   0     FB2_13        (b)     (b)
n_n510                5       4<- \/4   0     FB2_14  81    I/O     I
n_n446                8       4<- \/1   0     FB2_15  82    I/O     I
n_n585                3       1<- \/3   0     FB2_16  83    I/O     I
N18/N18_D2            8       3<-   0   0     FB2_17  84    I/O     I
n_n584                2       0   \/3   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$281   13: n_n396/n_n396_D2  25: n_n525 
  2: $OpTx$FX_DC$314   14: n_n428            26: n_n526 
  3: ADDATA0           15: n_n429            27: n_n527 
  4: ADDATA1           16: n_n430            28: n_n528 
  5: ADDATA2           17: n_n444            29: n_n541 
  6: BCD2P1            18: n_n445            30: n_n542 
  7: BCD2P2            19: n_n446            31: n_n543 
  8: BCD2P3            20: n_n487/n_n487_D2  32: n_n544 
  9: N12/N12_D2        21: n_n509            33: n_n567/n_n567_D2 
 10: N16/N16_D2        22: n_n510            34: n_n583 
 11: n_n122            23: n_n511            35: n_n584 
 12: n_n123            24: n_n512            36: n_n585 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
N14/N14_D2           ..XXX.....XXX...........XXXX............ 10      10
n_n567/n_n567_D2     X.......X.XX........X...XX.............. 7       7
n_n544               ..........XX................XXXX........ 6       6
n_n541               ..........XX................XXXX........ 6       6
$OpTx$FX_DC$281      ..........XX................XXXX........ 6       6
n_n542               ..........XX................XXXX........ 6       6
n_n525               X.........XX........X...X............... 5       5
n_n543               ..........XX................XXXX........ 6       6
n_n526               X.......X.XX........X...X............... 6       6
N16/N16_D2           X.........XX..........X.....XXXXX....... 9       9
N12/N12_D2           X.........XX.........X...X..XXXX........ 9       9
n_n512               .......X..XX..........X.....XXXX........ 8       8
n_n511               ......X...XX.........X......XXXX........ 8       8
n_n510               .....X....XX........X.......XXXX........ 8       8
n_n446               .X........XX.XXXXXXX.................... 10      10
n_n585               ..........XX.....................XXX.... 5       5
N18/N18_D2           X........XXX...........X..X.XXXXX....... 11      11
n_n584               ..........XX.....................XX..... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
n_n509                1       0   \/2   2     FB3_1         (b)     (b)
BCD1P1                5       2<- \/2   0     FB3_2   14    I/O     O
BCD1P2                9       4<-   0   0     FB3_3   15    I/O     O
n_n349/n_n349_D216_   3       0   /\2   0     FB3_4         (b)     (b)
BCD1P3                3       0   \/1   1     FB3_5   17    I/O     O
BCD2P0                2       1<- \/4   0     FB3_6   18    I/O     O
n_n273               12       7<-   0   0     FB3_7         (b)     (b)
BCD2P1                2       0   /\3   0     FB3_8   19    I/O     O
BCD2P2                5       0     0   0     FB3_9   20    I/O     O
n_n272               10       5<-   0   0     FB3_10        (b)     (b)
BCD2P3                3       3<- /\5   0     FB3_11  21    I/O     O
(unused)              0       0   /\3   2     FB3_12  23    I/O     (b)
n_n288                2       0   \/1   2     FB3_13        (b)     (b)
n_n396/n_n396_D2      2       1<- \/4   0     FB3_14  24    I/O     (b)
n_n271                8       4<- \/1   0     FB3_15  25    I/O     (b)
n_n503                2       1<- \/4   0     FB3_16  26    I/O     (b)
n_n274               13       8<-   0   0     FB3_17  31    I/O     (b)
n_n125                1       0   /\4   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$289   13: N4/N4_D2          25: n_n287 
  2: $OpTx$FX_DC$297   14: N5/N5_D2          26: n_n288 
  3: $OpTx$FX_DC$299   15: RESET0            27: n_n289 
  4: BCD1P1            16: n_n122            28: n_n290 
  5: BCD1P2            17: n_n123            29: n_n311/n_n311_D2 
  6: BCD1P3            18: n_n268            30: n_n502 
  7: BCD2P0            19: n_n269            31: n_n503 
  8: BCD2P1            20: n_n270            32: n_n527 
  9: BCD2P2            21: n_n271            33: n_n541 
 10: BCD2P3            22: n_n272            34: n_n542 
 11: N169/N169_D2      23: n_n273            35: n_n543 
 12: N183/N183_D2      24: n_n274            36: n_n544 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
n_n509               ......X........XX...............XXXX.... 7       7
BCD1P1               X..X..X......XXXX........X.............. 8       8
BCD1P2               X...X.XX.....XXXX........XX............. 10      10
n_n349/n_n349_D216_  X.....XX......XXX........XX............. 8       8
BCD1P3               X.X..X.......XX............X............ 6       6
BCD2P0               X.....X.....X.X.........X............... 5       5
n_n273               X.........XX..XXXXXXXXX.....X........... 13      13
BCD2P1               X......X....X.X..........X.............. 5       5
BCD2P2               X.....XXX...X.XXX........XX............. 10      10
n_n272               X.........XX..XXXXXXXX......X........... 12      12
BCD2P3               X.X......X..X.X............X............ 6       6
n_n288               X.........X...X.........XX..X........... 6       6
n_n396/n_n396_D2     .X.............XX..............X........ 4       4
n_n271               X.........XX..XXXXXXX.......X........... 11      11
n_n503               ...............XX............XX......... 4       4
n_n274               X.........X...XXXXXXXXXX....X........... 13      13
n_n125               ...............X........................ 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\3   2     FB4_1         (b)     (b)
n_n126                1       0     0   4     FB4_2   57    I/O     (b)
n_n275                2       0     0   3     FB4_3   58    I/O     (b)
n_n268                2       0     0   3     FB4_4         (b)     (b)
n_n267                2       0     0   3     FB4_5   61    I/O     (b)
n_n712/n_n712_D2      3       0     0   2     FB4_6   62    I/O     (b)
n_n282                3       0     0   2     FB4_7         (b)     (b)
n_n281                3       0     0   2     FB4_8   63    I/O     (b)
n_n280                3       0     0   2     FB4_9   65    I/O     (b)
n_n279                3       0     0   2     FB4_10        (b)     (b)
n_n278                3       0     0   2     FB4_11  66    I/O     (b)
n_n277                3       0     0   2     FB4_12  67    I/O     (b)
n_n276                3       0     0   2     FB4_13        (b)     (b)
$OpTx$FX_DC$297       4       0     0   1     FB4_14  68    I/O     (b)
n_n269                5       0     0   0     FB4_15  69    I/O     (b)
N183/N183_D2          5       0     0   0     FB4_16        (b)     (b)
n_n270                6       1<-   0   0     FB4_17  70    I/O     (b)
N96/N96_D2            7       3<- /\1   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$289   13: n_n122            25: n_n275 
  2: ADDATA0           14: n_n123            26: n_n276 
  3: ADDATA1           15: n_n125            27: n_n277 
  4: ADDATA2           16: n_n126            28: n_n278 
  5: ADDATA3           17: n_n267            29: n_n279 
  6: ADDATA4           18: n_n268            30: n_n280 
  7: ADDATA5           19: n_n269            31: n_n281 
  8: ADDATA6           20: n_n270            32: n_n282 
  9: ADDATA7           21: n_n271            33: n_n311/n_n311_D2 
 10: N169/N169_D2      22: n_n272            34: n_n445 
 11: N183/N183_D2      23: n_n273            35: n_n525 
 12: RESET0            24: n_n274            36: n_n526 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
n_n126               .............X.......................... 1       1
n_n275               XX.......X.X............X.......X....... 6       6
n_n268               X........X.X....XX..............X....... 6       6
n_n267               X........X.X....X..............XX....... 6       6
n_n712/n_n712_D2     ............XXXX........................ 4       4
n_n282               X.......XX.X..................XXX....... 7       7
n_n281               X......X.X.X.................XX.X....... 7       7
n_n280               X.....X..X.X................XX..X....... 7       7
n_n279               X....X...X.X...............XX...X....... 7       7
n_n278               X...X....X.X..............XX....X....... 7       7
n_n277               X..X.....X.X.............XX.....X....... 7       7
n_n276               X.X......X.X............XX......X....... 7       7
$OpTx$FX_DC$297      .XXX........XX....................XX.... 7       7
n_n269               X........XXXXX...XX.............X....... 9       9
N183/N183_D2         X..........XXX...XXXXXXX................ 11      11
n_n270               X........XXXXX...XXX............X....... 10      10
N96/N96_D2           .XX.........XX...................XXX.... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
n_n428                1       0   /\4   0     FB5_1         (b)     (b)
N193/N193_D2          1       0     0   4     FB5_2   32    I/O     (b)
n_n463                2       0     0   3     FB5_3   33    I/O     (b)
n_n460                2       0     0   3     FB5_4         (b)     (b)
$OpTx$FX_DC$314       2       0     0   3     FB5_5   34    I/O     (b)
n_n586                3       0     0   2     FB5_6   35    I/O     (b)
n_n583                3       0     0   2     FB5_7         (b)     (b)
n_n505                3       0     0   2     FB5_8   36    I/O     (b)
n_n504                3       0     0   2     FB5_9   37    I/O     (b)
n_n502                3       0     0   2     FB5_10        (b)     (b)
n_n461                3       0     0   2     FB5_11  39    I/O     (b)
n_n462                4       0     0   1     FB5_12  40    I/O     (b)
$OpTx$FX_DC$289       4       0     0   1     FB5_13        (b)     (b)
n_n431                5       0     0   0     FB5_14  41    I/O     (b)
n_n430                5       0     0   0     FB5_15  43    I/O     (b)
n_n429                5       0     0   0     FB5_16        (b)     (b)
n_n447                6       1<-   0   0     FB5_17  44    I/O     (b)
N98/N98_D2            8       4<- /\1   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$314   12: n_n429            22: n_n502 
  2: BCD1P0            13: n_n430            23: n_n503 
  3: BCD1P1            14: n_n431            24: n_n504 
  4: BCD1P2            15: n_n446            25: n_n505 
  5: BCD1P3            16: n_n447            26: n_n583 
  6: n_n122            17: n_n460            27: n_n584 
  7: n_n123            18: n_n461            28: n_n585 
  8: n_n125            19: n_n462            29: n_n586 
  9: n_n126            20: n_n463            30: n_n612/n_n612_D2 
 10: n_n396/n_n396_D2  21: n_n487/n_n487_D2  31: n_n712/n_n712_D2 
 11: n_n428           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
n_n428               .X...XX.........XXXX.................... 7       7
N193/N193_D2         .....XX..............XXXXXXXX........... 10      10
n_n463               .....XX.........XXXX.................... 6       6
n_n460               .....XX.........XXXX.................... 6       6
$OpTx$FX_DC$314      .....XX.........XXXX.................... 6       6
n_n586               .....XX..................XXXX........... 6       6
n_n583               .....XX..................XXXX........... 6       6
n_n505               .....XX..............XXXX............... 6       6
n_n504               .....XX..............XXX................ 5       5
n_n502               .....XX..............XXXX............... 6       6
n_n461               .....XX.........XXXX.................... 6       6
n_n462               .....XX.........XXXX.................... 6       6
$OpTx$FX_DC$289      .....XXXX.....................X......... 5       5
n_n431               ....XXX.....X...XXXX.................... 8       8
n_n430               ...X.XX....X....XXXX.................... 8       8
n_n429               ..X..XX...X.....XXXX.................... 8       8
n_n447               X....XX......X.XXXXXX................... 10      10
N98/N98_D2           .....XX..X....XX.............X.......... 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
N5/N5_D2              1       0     0   4     FB6_1         (b)     (b)
N4/N4_D2              1       0     0   4     FB6_2   45    I/O     (b)
n_n340                2       0     0   3     FB6_3   46    I/O     (b)
n_n290                2       0     0   3     FB6_4         (b)     (b)
n_n289                2       0     0   3     FB6_5   47    I/O     (b)
n_n287                2       0     0   3     FB6_6   48    I/O     (b)
n_n286                2       0     0   3     FB6_7         (b)     (b)
n_n283                2       0     0   3     FB6_8   50    I/O     (b)
n_n150                2       0     0   3     FB6_9   51    I/O     (b)
n_n149                2       0     0   3     FB6_10        (b)     (b)
N169/N169_D2          2       0     0   3     FB6_11  52    I/O     (b)
n_n342                3       0     0   2     FB6_12  53    I/O     (b)
n_n341                3       0     0   2     FB6_13        (b)     (b)
n_n339                3       0     0   2     FB6_14  54    I/O     (b)
n_n311/n_n311_D2      3       0     0   2     FB6_15  55    I/O     (b)
n_n285                3       0     0   2     FB6_16        (b)     (b)
n_n284                3       0     0   2     FB6_17  56    I/O     (b)
n_n122                4       0     0   1     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$289    9: n_n149            17: n_n289 
  2: N169/N169_D2      10: n_n150            18: n_n290 
  3: N183/N183_D2      11: n_n283            19: n_n311/n_n311_D2 
  4: N5/N5_D2          12: n_n284            20: n_n339 
  5: REQ0              13: n_n285            21: n_n340 
  6: RESET0            14: n_n286            22: n_n341 
  7: n_n122            15: n_n287            23: n_n342 
  8: n_n123            16: n_n288           

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
N5/N5_D2             X.....XX...........XXXX................. 7       7
N4/N4_D2             X.....XX...........XXXX................. 7       7
n_n340               X....X.............XX................... 4       4
n_n290               XX...X..........XXX..................... 6       6
n_n289               XX...X.........XX.X..................... 6       6
n_n287               XXX..X........X...X..................... 6       6
n_n286               X....X....XXXX.......................... 6       6
n_n283               XX...X....X............................. 4       4
n_n150               .....X..XX.............................. 3       3
n_n149               ....XXXXXX.............................. 6       6
N169/N169_D2         X....X....XXXX.......................... 6       6
n_n342               X....X.............XXXX................. 6       6
n_n341               X....X.............XXX.................. 5       5
n_n339               X....X.............XXXX................. 6       6
n_n311/n_n311_D2     X....X....XXXX.......................... 6       6
n_n285               X....X....XXXX.......................... 6       6
n_n284               XX...X....XX............................ 5       5
n_n122               X..X.XX.XX.........XXXX................. 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$281 <= ((NOT n_n122 AND n_n123 AND n_n541 AND n_n542 AND NOT n_n544)
	OR (NOT n_n122 AND n_n123 AND n_n542 AND n_n543 AND NOT n_n544));


$OpTx$FX_DC$289 <= n_n712/n_n712_D2
	 XOR 
$OpTx$FX_DC$289 <= ((NOT n_n123 AND n_n126)
	OR (NOT n_n122 AND NOT n_n123 AND n_n125)
	OR (NOT n_n122 AND n_n125 AND n_n126));


$OpTx$FX_DC$297 <= NOT (ADDATA2
	 XOR 
$OpTx$FX_DC$297 <= NOT (((NOT n_n122 AND n_n123 AND n_n526 AND NOT ADDATA1)
	OR (NOT n_n122 AND n_n123 AND n_n526 AND n_n525 AND NOT ADDATA0)
	OR (NOT n_n122 AND n_n123 AND n_n525 AND NOT ADDATA0 AND NOT ADDATA1)));


$OpTx$FX_DC$299 <= NOT (n_n349/n_n349_D216_
	 XOR 
$OpTx$FX_DC$299 <= NOT (((BCD2P0 AND NOT BCD2P2 AND n_n122 AND NOT n_n123)
	OR (NOT BCD2P0 AND BCD2P2 AND n_n122 AND NOT n_n123)));


$OpTx$FX_DC$314 <= ((NOT n_n122 AND n_n123 AND NOT n_n460 AND n_n461 AND NOT n_n462 AND 
	NOT n_n463)
	OR (NOT n_n122 AND n_n123 AND NOT n_n460 AND NOT n_n461 AND n_n462 AND 
	NOT n_n463));

FDCPE_ACK0: FDCPE port map (ACK0,ACK0_D,clk,'0','0');
ACK0_D <= (NOT RESET0 AND n_n122 AND n_n123 AND NOT n_n159 AND ACK0);

FDCPE_BCD0P0: FDCPE port map (BCD0P0,BCD0P0_D,clk,'0','0');
BCD0P0_D <= ((EXP1_.EXP)
	OR (NOT RESET0 AND BCD0P0 AND NOT N193/N193_D2));

FDCPE_BCD0P1: FDCPE port map (BCD0P1,BCD0P1_D,clk,'0','0');
BCD0P1_D <= ((RESET0)
	OR (n_n144.EXP)
	OR (NOT BCD0P1 AND NOT N193/N193_D2)
	OR (NOT n_n444 AND N193/N193_D2 AND N96/N96_D2));

FDCPE_BCD0P2: FDCPE port map (BCD0P2,BCD0P2_D,clk,'0','0');
BCD0P2_D <= ((EXP2_.EXP)
	OR (EXP3_.EXP)
	OR (NOT RESET0 AND BCD0P2 AND NOT N193/N193_D2)
	OR (NOT RESET0 AND n_n122 AND n_n446 AND N193/N193_D2 AND 
	NOT n_n396/n_n396_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n446 AND N193/N193_D2 AND 
	n_n396/n_n396_D2)
	OR (NOT RESET0 AND NOT n_n123 AND n_n446 AND N193/N193_D2 AND 
	NOT n_n396/n_n396_D2)
	OR (NOT RESET0 AND NOT n_n123 AND NOT n_n446 AND N193/N193_D2 AND 
	n_n396/n_n396_D2));

FDCPE_BCD0P3: FDCPE port map (BCD0P3,BCD0P3_D,clk,'0','0');
BCD0P3_D <= ((n_n123.EXP)
	OR (n_n445.EXP)
	OR (NOT RESET0 AND BCD0P3 AND NOT N193/N193_D2)
	OR (NOT RESET0 AND n_n122 AND N193/N193_D2 AND NOT N98/N98_D2)
	OR (NOT RESET0 AND NOT n_n123 AND N193/N193_D2 AND NOT N98/N98_D2)
	OR (NOT RESET0 AND ADDATA3 AND N193/N193_D2 AND NOT N14/N14_D2 AND 
	NOT N98/N98_D2)
	OR (NOT RESET0 AND NOT ADDATA3 AND N193/N193_D2 AND N14/N14_D2 AND 
	NOT N98/N98_D2));

FDCPE_BCD1P0: FDCPE port map (BCD1P0,BCD1P0_D,clk,'0','0');
BCD1P0_D <= ((NOT RESET0 AND BCD1P0 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND n_n287 AND NOT $OpTx$FX_DC$289 AND N5/N5_D2));

FDCPE_BCD1P1: FDCPE port map (BCD1P1,BCD1P1_D,clk,'0','0');
BCD1P1_D <= ((n_n509.EXP)
	OR (NOT RESET0 AND BCD1P1 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND BCD2P0 AND NOT n_n288 AND NOT $OpTx$FX_DC$289 AND 
	N5/N5_D2)
	OR (NOT RESET0 AND NOT BCD2P0 AND n_n288 AND NOT $OpTx$FX_DC$289 AND 
	N5/N5_D2));

FDCPE_BCD1P2: FDCPE port map (BCD1P2,BCD1P2_D,clk,'0','0');
BCD1P2_D <= ((n_n140.EXP)
	OR (n_n349/n_n349_D216_.EXP)
	OR (NOT RESET0 AND BCD1P2 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND NOT BCD2P1 AND NOT BCD2P0 AND n_n289 AND 
	NOT $OpTx$FX_DC$289 AND N5/N5_D2)
	OR (NOT RESET0 AND BCD2P1 AND NOT BCD2P0 AND n_n122 AND NOT n_n123 AND 
	NOT n_n289 AND NOT $OpTx$FX_DC$289 AND N5/N5_D2)
	OR (NOT RESET0 AND BCD2P1 AND n_n122 AND NOT n_n123 AND NOT n_n289 AND 
	n_n288 AND NOT $OpTx$FX_DC$289 AND N5/N5_D2)
	OR (NOT RESET0 AND NOT BCD2P1 AND BCD2P0 AND n_n122 AND NOT n_n123 AND 
	NOT n_n289 AND NOT n_n288 AND NOT $OpTx$FX_DC$289 AND N5/N5_D2));

FDCPE_BCD1P3: FDCPE port map (BCD1P3,BCD1P3_D,clk,'0','0');
BCD1P3_D <= ((NOT RESET0 AND BCD1P3 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND n_n290 AND NOT $OpTx$FX_DC$289 AND 
	$OpTx$FX_DC$299 AND N5/N5_D2)
	OR (NOT RESET0 AND NOT n_n290 AND NOT $OpTx$FX_DC$289 AND 
	NOT $OpTx$FX_DC$299 AND N5/N5_D2));

FDCPE_BCD2P0: FDCPE port map (BCD2P0,BCD2P0_D,clk,'0','0');
BCD2P0_D <= ((n_n142.EXP)
	OR (NOT RESET0 AND BCD2P0 AND NOT N4/N4_D2));

FDCPE_BCD2P1: FDCPE port map (BCD2P1,BCD2P1_D,clk,'0','0');
BCD2P1_D <= ((NOT RESET0 AND BCD2P1 AND NOT N4/N4_D2)
	OR (NOT RESET0 AND n_n288 AND NOT $OpTx$FX_DC$289 AND N4/N4_D2));

FDCPE_BCD2P2: FDCPE port map (BCD2P2,BCD2P2_D,clk,'0','0');
BCD2P2_D <= ((NOT RESET0 AND BCD2P2 AND NOT N4/N4_D2)
	OR (NOT RESET0 AND NOT n_n122 AND n_n289 AND NOT $OpTx$FX_DC$289 AND 
	N4/N4_D2)
	OR (NOT RESET0 AND n_n123 AND n_n289 AND NOT $OpTx$FX_DC$289 AND 
	N4/N4_D2)
	OR (NOT RESET0 AND NOT BCD2P1 AND NOT BCD2P0 AND n_n289 AND 
	NOT $OpTx$FX_DC$289 AND N4/N4_D2)
	OR (NOT RESET0 AND NOT BCD2P1 AND n_n289 AND n_n288 AND 
	NOT $OpTx$FX_DC$289 AND N4/N4_D2));

FDCPE_BCD2P3: FDCPE port map (BCD2P3,EXP0_.EXP,clk,'0','0');












N12/N12_D2 <= ((N16/N16_D2.EXP)
	OR (n_n526 AND NOT n_n510));


N14/N14_D2 <= ((n_n567/n_n567_D2.EXP)
	OR (n_n584.EXP)
	OR (n_n122 AND NOT n_n528)
	OR (NOT n_n123 AND NOT n_n528)
	OR (NOT n_n527 AND NOT n_n528 AND ADDATA2)
	OR (n_n528 AND NOT ADDATA2 AND n_n396/n_n396_D2)
	OR (NOT n_n528 AND ADDATA0 AND ADDATA1 AND NOT n_n396/n_n396_D2));


N16/N16_D2 <= ((n_n526.EXP)
	OR (NOT n_n511 AND n_n567/n_n567_D2)
	OR (NOT $OpTx$FX_DC$281 AND n_n567/n_n567_D2));


N169/N169_D2 <= ((NOT RESET0 AND n_n285 AND n_n286 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n283 AND n_n284 AND n_n286 AND 
	NOT $OpTx$FX_DC$289));


N18/N18_D2 <= ((n_n585.EXP)
	OR (NOT n_n512 AND NOT N16/N16_D2 AND n_n567/n_n567_D2)
	OR (NOT $OpTx$FX_DC$281 AND NOT N16/N16_D2 AND n_n567/n_n567_D2)
	OR (NOT n_n122 AND n_n123 AND n_n527 AND NOT n_n512 AND N16/N16_D2)
	OR (NOT n_n122 AND n_n123 AND n_n527 AND NOT $OpTx$FX_DC$281 AND 
	N16/N16_D2)
	OR (NOT n_n122 AND n_n123 AND NOT n_n527 AND n_n542 AND n_n543 AND 
	NOT n_n544 AND n_n512 AND N16/N16_D2));


N183/N183_D2 <= ((NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n272 AND NOT n_n274 AND 
	NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n273 AND NOT n_n274 AND 
	NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n269 AND NOT n_n270 AND 
	NOT n_n271 AND NOT n_n274 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n123 AND NOT n_n270 AND NOT n_n272 AND NOT n_n271 AND 
	NOT n_n273 AND NOT n_n274 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n123 AND NOT n_n269 AND NOT n_n268 AND NOT n_n272 AND 
	NOT n_n271 AND NOT n_n273 AND NOT n_n274 AND NOT $OpTx$FX_DC$289));


N193/N193_D2 <= (NOT n_n122 AND n_n123 AND NOT n_n502 AND NOT n_n504 AND NOT n_n583 AND 
	NOT n_n585 AND n_n503 AND n_n584 AND n_n505 AND n_n586);


N4/N4_D2 <= (NOT n_n122 AND NOT n_n123 AND NOT n_n339 AND n_n341 AND NOT n_n340 AND 
	n_n342 AND NOT $OpTx$FX_DC$289);


N5/N5_D2 <= (n_n122 AND NOT n_n123 AND NOT n_n339 AND n_n341 AND NOT n_n340 AND 
	n_n342 AND NOT $OpTx$FX_DC$289);


N96/N96_D2 <= NOT (n_n445
	 XOR 
N96/N96_D2 <= NOT (((EXP4_.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n526 AND NOT n_n525 AND NOT ADDATA1)
	OR (NOT n_n122 AND n_n123 AND n_n526 AND ADDATA0 AND NOT ADDATA1)
	OR (NOT n_n122 AND n_n123 AND NOT n_n526 AND ADDATA0 AND ADDATA1)));


N98/N98_D2 <= ((n_n428.EXP)
	OR (n_n122 AND NOT n_n447)
	OR (NOT n_n123 AND NOT n_n447)
	OR (NOT n_n446 AND NOT n_n447 AND NOT n_n612/n_n612_D2)
	OR (NOT n_n447 AND n_n396/n_n396_D2 AND NOT n_n612/n_n612_D2));

FDCPE_n_n122: FDCPE port map (n_n122,n_n122_D,clk,'0','0');
n_n122_D <= ((NOT RESET0 AND n_n122 AND n_n150 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n149 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND NOT n_n339 AND n_n341 AND n_n150 AND NOT n_n340 AND 
	n_n342 AND NOT $OpTx$FX_DC$289 AND NOT N5/N5_D2)
	OR (NOT RESET0 AND NOT n_n339 AND n_n341 AND NOT n_n340 AND NOT n_n149 AND 
	n_n342 AND NOT $OpTx$FX_DC$289 AND NOT N5/N5_D2));

FDCPE_n_n123: FDCPE port map (n_n123,n_n123_D,clk,'0','0');
n_n123_D <= ((RESET0)
	OR (FC_0_.OUT)
	OR (NOT n_n123 AND $OpTx$FX_DC$289)
	OR (NOT n_n123 AND NOT N5/N5_D2));

FDCPE_n_n125: FDCPE port map (n_n125,n_n122,clk,'0','0');

FDCPE_n_n126: FDCPE port map (n_n126,n_n123,clk,'0','0');

FDCPE_n_n149: FDCPE port map (n_n149,n_n149_D,clk,'0','0');
n_n149_D <= ((NOT REQ0 AND NOT RESET0 AND NOT n_n150 AND NOT n_n149)
	OR (REQ0 AND NOT RESET0 AND n_n122 AND n_n123 AND n_n150 AND 
	NOT n_n149));

FDCPE_n_n150: FDCPE port map (n_n150,n_n150_D,clk,'0','0');
n_n150_D <= ((NOT RESET0 AND n_n150 AND NOT n_n149)
	OR (NOT RESET0 AND NOT n_n150 AND n_n149));

FDCPE_n_n159: FDCPE port map (n_n159,n_n159_D,clk,'0','0');
n_n159_D <= ((NOT RESET0 AND NOT n_n159 AND NOT ACK0)
	OR (NOT RESET0 AND n_n122 AND n_n123 AND n_n159 AND ACK0));

FDCPE_n_n267: FDCPE port map (n_n267,n_n267_D,clk,'0','0');
n_n267_D <= ((n_n267 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n282 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n268: FDCPE port map (n_n268,n_n268_D,clk,'0','0');
n_n268_D <= ((n_n268 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n267 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n269: FDCPE port map (n_n269,n_n269_D,clk,'0','0');
n_n269_D <= ((n_n269 AND N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND n_n268 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n123 AND n_n268 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n268 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n268 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2));

FDCPE_n_n270: FDCPE port map (n_n270,n_n270_D,clk,'0','0');
n_n270_D <= ((N96/N96_D2.EXP)
	OR (n_n270 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n123 AND n_n269 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n269 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND n_n269 AND n_n268 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n269 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2));

FDCPE_n_n271: FDCPE port map (n_n271,n_n271_D,clk,'0','0');
n_n271_D <= ((n_n396/n_n396_D2.EXP)
	OR (NOT RESET0 AND n_n270 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND n_n269 AND NOT n_n270 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n270 AND n_n268 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n269 AND NOT n_n270 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2));

FDCPE_n_n272: FDCPE port map (n_n272,n_n272_D,clk,'0','0');
n_n272_D <= ((n_n137.EXP)
	OR (n_n272 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n123 AND n_n271 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n271 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND n_n270 AND n_n271 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n270 AND n_n268 AND n_n271 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n273: FDCPE port map (n_n273,n_n273_D,clk,'0','0');
n_n273_D <= ((n_n134.EXP)
	OR (n_n135.EXP)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND n_n269 AND NOT n_n272 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND n_n270 AND NOT n_n272 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND NOT n_n272 AND n_n271 AND 
	NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n270 AND NOT n_n272 AND 
	NOT n_n271 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND 
	NOT N183/N183_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n269 AND NOT n_n268 AND 
	NOT n_n272 AND NOT n_n271 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND 
	NOT N183/N183_D2 AND NOT N169/N169_D2));

FDCPE_n_n274: FDCPE port map (n_n274,n_n274_D,clk,'0','0');
n_n274_D <= ((n_n503.EXP)
	OR (n_n125.EXP)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND n_n269 AND n_n272 AND 
	NOT n_n273 AND n_n274 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND n_n270 AND n_n272 AND 
	NOT n_n273 AND n_n274 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2)
	OR (NOT RESET0 AND NOT n_n122 AND NOT n_n123 AND n_n272 AND n_n271 AND 
	NOT n_n273 AND n_n274 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n270 AND NOT n_n272 AND 
	NOT n_n271 AND NOT n_n273 AND n_n274 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2)
	OR (NOT RESET0 AND n_n122 AND NOT n_n123 AND NOT n_n269 AND NOT n_n268 AND 
	NOT n_n272 AND NOT n_n271 AND NOT n_n273 AND n_n274 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2));

FDCPE_n_n275: FDCPE port map (n_n275,n_n275_D,clk,'0','0');
n_n275_D <= ((n_n275 AND N169/N169_D2)
	OR (NOT RESET0 AND ADDATA0 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n276: FDCPE port map (n_n276,n_n276_D,clk,'0','0');
n_n276_D <= ((n_n276 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n275 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA1 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n277: FDCPE port map (n_n277,n_n277_D,clk,'0','0');
n_n277_D <= ((n_n277 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n276 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA2 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n278: FDCPE port map (n_n278,n_n278_D,clk,'0','0');
n_n278_D <= ((n_n278 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n277 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA3 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n279: FDCPE port map (n_n279,n_n279_D,clk,'0','0');
n_n279_D <= ((n_n279 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n278 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA4 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n280: FDCPE port map (n_n280,n_n280_D,clk,'0','0');
n_n280_D <= ((n_n280 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n279 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA5 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n281: FDCPE port map (n_n281,n_n281_D,clk,'0','0');
n_n281_D <= ((n_n281 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n280 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA6 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n282: FDCPE port map (n_n282,n_n282_D,clk,'0','0');
n_n282_D <= ((n_n282 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n281 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2)
	OR (NOT RESET0 AND ADDATA7 AND NOT $OpTx$FX_DC$289 AND 
	n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n283: FDCPE port map (n_n283,n_n283_D,clk,'0','0');
n_n283_D <= ((n_n283 AND N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n283 AND NOT $OpTx$FX_DC$289 AND 
	NOT N169/N169_D2));

FDCPE_n_n284: FDCPE port map (n_n284,n_n284_D,clk,'0','0');
n_n284_D <= ((n_n284 AND N169/N169_D2)
	OR (NOT RESET0 AND NOT n_n283 AND n_n284 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n283 AND NOT n_n284 AND NOT $OpTx$FX_DC$289 AND 
	NOT N169/N169_D2));

FTCPE_n_n285: FTCPE port map (n_n285,n_n285_T,clk,'0','0');
n_n285_T <= ((RESET0 AND n_n285)
	OR (n_n285 AND $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n283 AND n_n284 AND NOT n_n286 AND 
	NOT $OpTx$FX_DC$289));

FDCPE_n_n286: FDCPE port map (n_n286,n_n286_D,clk,'0','0');
n_n286_D <= ((NOT RESET0 AND n_n286 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n283 AND n_n284 AND n_n285 AND 
	NOT $OpTx$FX_DC$289));

FDCPE_n_n287: FDCPE port map (n_n287,n_n287_D,clk,'0','0');
n_n287_D <= ((n_n287 AND N169/N169_D2)
	OR (NOT RESET0 AND NOT $OpTx$FX_DC$289 AND NOT n_n311/n_n311_D2 AND 
	NOT N183/N183_D2 AND NOT N169/N169_D2));

FDCPE_n_n288: FDCPE port map (n_n288,n_n288_D,clk,'0','0');
n_n288_D <= ((n_n288 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n287 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n289: FDCPE port map (n_n289,n_n289_D,clk,'0','0');
n_n289_D <= ((n_n289 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n288 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));

FDCPE_n_n290: FDCPE port map (n_n290,n_n290_D,clk,'0','0');
n_n290_D <= ((n_n290 AND N169/N169_D2)
	OR (NOT RESET0 AND n_n289 AND NOT $OpTx$FX_DC$289 AND 
	NOT n_n311/n_n311_D2 AND NOT N169/N169_D2));


n_n311/n_n311_D2 <= ((RESET0)
	OR ($OpTx$FX_DC$289)
	OR (n_n283 AND NOT n_n284 AND NOT n_n285 AND NOT n_n286));

FDCPE_n_n339: FDCPE port map (n_n339,n_n339_D,clk,'0','0');
n_n339_D <= ((NOT RESET0 AND NOT n_n339 AND NOT n_n341 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n339 AND n_n340 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n339 AND NOT n_n342 AND NOT $OpTx$FX_DC$289));

FDCPE_n_n340: FDCPE port map (n_n340,n_n340_D,clk,'0','0');
n_n340_D <= ((NOT RESET0 AND n_n339 AND NOT n_n340 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND NOT n_n339 AND n_n340 AND NOT $OpTx$FX_DC$289));

FDCPE_n_n341: FDCPE port map (n_n341,n_n341_D,clk,'0','0');
n_n341_D <= ((NOT RESET0 AND NOT n_n339 AND n_n341 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n341 AND NOT n_n340 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n339 AND NOT n_n341 AND n_n340 AND 
	NOT $OpTx$FX_DC$289));

FTCPE_n_n342: FTCPE port map (n_n342,n_n342_T,clk,'0','0');
n_n342_T <= ((RESET0 AND n_n342)
	OR (n_n342 AND $OpTx$FX_DC$289)
	OR (NOT RESET0 AND n_n339 AND n_n341 AND n_n340 AND 
	NOT $OpTx$FX_DC$289));


n_n349/n_n349_D216_ <= ((NOT RESET0 AND BCD2P1 AND n_n122 AND NOT n_n123 AND NOT n_n289 AND 
	NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND BCD2P1 AND BCD2P0 AND n_n122 AND NOT n_n123 AND 
	NOT n_n288 AND NOT $OpTx$FX_DC$289)
	OR (NOT RESET0 AND BCD2P0 AND n_n122 AND NOT n_n123 AND NOT n_n289 AND 
	NOT n_n288 AND NOT $OpTx$FX_DC$289));


n_n396/n_n396_D2 <= ((n_n288.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n527 AND $OpTx$FX_DC$297));

FDCPE_n_n428: FDCPE port map (n_n428,n_n428_D,clk,'0','0');
n_n428_D <= (BCD1P0 AND NOT n_n122 AND n_n123 AND NOT n_n460 AND NOT n_n461 AND 
	NOT n_n462 AND NOT n_n463);

FDCPE_n_n429: FDCPE port map (n_n429,n_n429_D,clk,'0','0');
n_n429_D <= ((NOT n_n122 AND n_n123 AND n_n460 AND n_n428)
	OR (NOT n_n122 AND n_n123 AND n_n461 AND n_n428)
	OR (NOT n_n122 AND n_n123 AND n_n462 AND n_n428)
	OR (NOT n_n122 AND n_n123 AND n_n463 AND n_n428)
	OR (BCD1P1 AND NOT n_n122 AND n_n123 AND NOT n_n460 AND NOT n_n461 AND 
	NOT n_n462 AND NOT n_n463));

FDCPE_n_n430: FDCPE port map (n_n430,n_n430_D,clk,'0','0');
n_n430_D <= ((NOT n_n122 AND n_n123 AND n_n460 AND n_n429)
	OR (NOT n_n122 AND n_n123 AND n_n461 AND n_n429)
	OR (NOT n_n122 AND n_n123 AND n_n462 AND n_n429)
	OR (NOT n_n122 AND n_n123 AND n_n463 AND n_n429)
	OR (BCD1P2 AND NOT n_n122 AND n_n123 AND NOT n_n460 AND NOT n_n461 AND 
	NOT n_n462 AND NOT n_n463));

FDCPE_n_n431: FDCPE port map (n_n431,n_n431_D,clk,'0','0');
n_n431_D <= ((NOT n_n122 AND n_n123 AND n_n460 AND n_n430)
	OR (NOT n_n122 AND n_n123 AND n_n461 AND n_n430)
	OR (NOT n_n122 AND n_n123 AND n_n462 AND n_n430)
	OR (NOT n_n122 AND n_n123 AND n_n463 AND n_n430)
	OR (BCD1P3 AND NOT n_n122 AND n_n123 AND NOT n_n460 AND NOT n_n461 AND 
	NOT n_n462 AND NOT n_n463));

FDCPE_n_n444: FDCPE port map (n_n444,n_n444_D,clk,'0','0');
n_n444_D <= ((NOT n_n122 AND n_n123 AND n_n444 AND NOT n_n428)
	OR (NOT n_n122 AND n_n123 AND n_n444 AND NOT $OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND NOT n_n444 AND n_n428 AND 
	$OpTx$FX_DC$314));

FTCPE_n_n445: FTCPE port map (n_n445,n_n445_T,clk,'0','0');
n_n445_T <= ((n_n139.EXP)
	OR (n_n122 AND NOT n_n445)
	OR (NOT n_n123 AND NOT n_n445)
	OR (NOT n_n122 AND n_n123 AND NOT $OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND NOT n_n444 AND NOT n_n429));

FDCPE_n_n446: FDCPE port map (n_n446,n_n446_D,clk,'0','0');
n_n446_D <= ((n_n510.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n446 AND NOT n_n487/n_n487_D2)
	OR (NOT n_n122 AND n_n123 AND n_n430 AND $OpTx$FX_DC$314 AND 
	NOT n_n487/n_n487_D2)
	OR (NOT n_n122 AND n_n123 AND n_n445 AND n_n429 AND 
	$OpTx$FX_DC$314 AND NOT n_n487/n_n487_D2)
	OR (NOT n_n122 AND n_n123 AND n_n444 AND n_n428 AND n_n429 AND 
	$OpTx$FX_DC$314 AND NOT n_n487/n_n487_D2));

FTCPE_n_n447: FTCPE port map (n_n447,n_n447_T,clk,'0','0');
n_n447_T <= ((N98/N98_D2.EXP)
	OR (n_n122 AND NOT n_n447)
	OR (NOT n_n123 AND NOT n_n447)
	OR (NOT n_n122 AND n_n123 AND NOT n_n431 AND NOT n_n487/n_n487_D2)
	OR (NOT n_n122 AND n_n123 AND NOT $OpTx$FX_DC$314 AND 
	NOT n_n487/n_n487_D2)
	OR (NOT n_n122 AND n_n123 AND NOT n_n460 AND n_n461 AND NOT n_n462 AND 
	NOT n_n463 AND n_n431 AND n_n487/n_n487_D2));

FDCPE_n_n460: FDCPE port map (n_n460,n_n460_D,clk,'0','0');
n_n460_D <= ((NOT n_n122 AND n_n123 AND NOT n_n460)
	OR (NOT n_n122 AND n_n123 AND n_n461 AND n_n462 AND n_n463));

FDCPE_n_n461: FDCPE port map (n_n461,n_n461_D,clk,'0','0');
n_n461_D <= ((NOT n_n122 AND n_n123 AND n_n460 AND NOT n_n461)
	OR (NOT n_n122 AND n_n123 AND NOT n_n460 AND n_n461)
	OR (NOT n_n122 AND n_n123 AND n_n461 AND n_n462 AND n_n463));

FDCPE_n_n462: FDCPE port map (n_n462,n_n462_D,clk,'0','0');
n_n462_D <= ((NOT n_n122 AND n_n123 AND NOT n_n460 AND n_n462)
	OR (NOT n_n122 AND n_n123 AND NOT n_n461 AND n_n462)
	OR (NOT n_n122 AND n_n123 AND n_n460 AND n_n461 AND NOT n_n462)
	OR (NOT n_n122 AND n_n123 AND n_n460 AND n_n461 AND n_n463));

FDCPE_n_n463: FDCPE port map (n_n463,n_n463_D,clk,'0','0');
n_n463_D <= ((NOT n_n122 AND n_n123 AND n_n463)
	OR (NOT n_n122 AND n_n123 AND n_n460 AND n_n461 AND n_n462));


n_n487/n_n487_D2 <= ((n_n444.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n446 AND n_n430 AND 
	$OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND n_n445 AND n_n446 AND n_n429 AND 
	$OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND n_n445 AND n_n429 AND n_n430 AND 
	$OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND n_n445 AND n_n446 AND n_n444 AND 
	n_n428 AND $OpTx$FX_DC$314)
	OR (NOT n_n122 AND n_n123 AND n_n446 AND n_n444 AND n_n428 AND 
	n_n429 AND $OpTx$FX_DC$314));

FDCPE_n_n502: FDCPE port map (n_n502,n_n502_D,clk,'0','0');
n_n502_D <= ((NOT n_n122 AND n_n123 AND NOT n_n502 AND n_n504)
	OR (NOT n_n122 AND n_n123 AND NOT n_n502 AND NOT n_n503)
	OR (NOT n_n122 AND n_n123 AND NOT n_n502 AND NOT n_n505));

FDCPE_n_n503: FDCPE port map (n_n503,n_n503_D,clk,'0','0');
n_n503_D <= ((n_n271.EXP)
	OR (NOT n_n122 AND n_n123 AND NOT n_n502 AND n_n503));

FDCPE_n_n504: FDCPE port map (n_n504,n_n504_D,clk,'0','0');
n_n504_D <= ((NOT n_n122 AND n_n123 AND NOT n_n502 AND n_n504)
	OR (NOT n_n122 AND n_n123 AND n_n504 AND NOT n_n503)
	OR (NOT n_n122 AND n_n123 AND n_n502 AND NOT n_n504 AND n_n503));

FTCPE_n_n505: FTCPE port map (n_n505,n_n505_T,clk,'0','0');
n_n505_T <= ((n_n122 AND n_n505)
	OR (NOT n_n123 AND n_n505)
	OR (NOT n_n122 AND n_n123 AND n_n502 AND n_n504 AND n_n503));

FDCPE_n_n509: FDCPE port map (n_n509,n_n509_D,clk,'0','0');
n_n509_D <= (BCD2P0 AND NOT n_n122 AND n_n123 AND NOT n_n541 AND NOT n_n542 AND 
	NOT n_n543 AND NOT n_n544);

FDCPE_n_n510: FDCPE port map (n_n510,n_n510_D,clk,'0','0');
n_n510_D <= ((n_n511.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n509));

FDCPE_n_n511: FDCPE port map (n_n511,n_n511_D,clk,'0','0');
n_n511_D <= ((n_n512.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n510));

FDCPE_n_n512: FDCPE port map (n_n512,n_n512_D,clk,'0','0');
n_n512_D <= ((N12/N12_D2.EXP)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n511));

FDCPE_n_n525: FDCPE port map (n_n525,n_n525_D,clk,'0','0');
n_n525_D <= ((NOT n_n122 AND n_n123 AND n_n525 AND NOT n_n509)
	OR (NOT n_n122 AND n_n123 AND n_n525 AND NOT $OpTx$FX_DC$281)
	OR (NOT n_n122 AND n_n123 AND NOT n_n525 AND n_n509 AND 
	$OpTx$FX_DC$281));

FDCPE_n_n526: FDCPE port map (n_n526,n_n526_D,clk,'0','0');
n_n526_D <= ((n_n543.EXP)
	OR (NOT n_n122 AND n_n123 AND NOT n_n525 AND N12/N12_D2)
	OR (NOT n_n122 AND n_n123 AND NOT n_n509 AND N12/N12_D2)
	OR (NOT n_n122 AND n_n123 AND N12/N12_D2 AND NOT $OpTx$FX_DC$281));

FDCPE_n_n527: FDCPE port map (n_n527,n_n527_D,clk,'0','0');
n_n527_D <= ((NOT n_n122 AND n_n123 AND n_n527 AND NOT N16/N16_D2)
	OR (NOT n_n122 AND n_n123 AND NOT n_n527 AND N16/N16_D2));

FDCPE_n_n528: FDCPE port map (n_n528,n_n528_D,clk,'0','0');
n_n528_D <= ((NOT n_n122 AND n_n123 AND n_n528 AND NOT N18/N18_D2)
	OR (NOT n_n122 AND n_n123 AND NOT n_n528 AND N18/N18_D2));

FDCPE_n_n541: FDCPE port map (n_n541,n_n541_D,clk,'0','0');
n_n541_D <= ((NOT n_n122 AND n_n123 AND NOT n_n541)
	OR (NOT n_n122 AND n_n123 AND n_n542 AND n_n543 AND n_n544));

FDCPE_n_n542: FDCPE port map (n_n542,n_n542_D,clk,'0','0');
n_n542_D <= ((NOT n_n122 AND n_n123 AND n_n541 AND NOT n_n542)
	OR (NOT n_n122 AND n_n123 AND NOT n_n541 AND n_n542)
	OR (NOT n_n122 AND n_n123 AND n_n542 AND n_n543 AND n_n544));

FDCPE_n_n543: FDCPE port map (n_n543,n_n543_D,clk,'0','0');
n_n543_D <= ((NOT n_n122 AND n_n123 AND NOT n_n541 AND n_n543)
	OR (NOT n_n122 AND n_n123 AND NOT n_n542 AND n_n543)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n542 AND NOT n_n543)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n542 AND n_n544));

FDCPE_n_n544: FDCPE port map (n_n544,n_n544_D,clk,'0','0');
n_n544_D <= ((NOT n_n122 AND n_n123 AND n_n544)
	OR (NOT n_n122 AND n_n123 AND n_n541 AND n_n542 AND n_n543));


n_n567/n_n567_D2 <= ((n_n544.EXP)
	OR (n_n526 AND NOT N12/N12_D2));

FDCPE_n_n583: FDCPE port map (n_n583,n_n583_D,clk,'0','0');
n_n583_D <= ((NOT n_n122 AND n_n123 AND NOT n_n583 AND n_n585)
	OR (NOT n_n122 AND n_n123 AND NOT n_n583 AND NOT n_n584)
	OR (NOT n_n122 AND n_n123 AND NOT n_n583 AND NOT n_n586));

FDCPE_n_n584: FDCPE port map (n_n584,n_n584_D,clk,'0','0');
n_n584_D <= ((NOT n_n122 AND n_n123 AND n_n583 AND NOT n_n584)
	OR (NOT n_n122 AND n_n123 AND NOT n_n583 AND n_n584));

FDCPE_n_n585: FDCPE port map (n_n585,n_n585_D,clk,'0','0');
n_n585_D <= ((n_n446.EXP)
	OR (NOT n_n122 AND n_n123 AND NOT n_n583 AND n_n585)
	OR (NOT n_n122 AND n_n123 AND n_n585 AND NOT n_n584));

FTCPE_n_n586: FTCPE port map (n_n586,n_n586_T,clk,'0','0');
n_n586_T <= ((n_n122 AND n_n586)
	OR (NOT n_n123 AND n_n586)
	OR (NOT n_n122 AND n_n123 AND n_n583 AND n_n585 AND n_n584));


n_n612/n_n612_D2 <= ((NOT n_n122 AND n_n123 AND n_n445 AND NOT N96/N96_D2)
	OR (NOT n_n122 AND n_n123 AND n_n444 AND n_n525 AND ADDATA0 AND 
	N96/N96_D2)
	OR (NOT n_n122 AND n_n123 AND n_n444 AND NOT n_n525 AND NOT ADDATA0 AND 
	N96/N96_D2));


n_n712/n_n712_D2 <= ((n_n123 AND NOT n_n126)
	OR (n_n122 AND n_n123 AND NOT n_n125)
	OR (n_n122 AND NOT n_n125 AND NOT n_n126));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ADDATA5                          43 TIE                           
  2 ADDATA6                          44 TIE                           
  3 ADDATA7                          45 TIE                           
  4 ACK0                             46 TIE                           
  5 BCD0P0                           47 TIE                           
  6 BCD0P1                           48 TIE                           
  7 BCD0P2                           49 GND                           
  8 GND                              50 TIE                           
  9 clk                              51 TIE                           
 10 TIE                              52 TIE                           
 11 BCD0P3                           53 TIE                           
 12 TIE                              54 TIE                           
 13 BCD1P0                           55 TIE                           
 14 BCD1P1                           56 TIE                           
 15 BCD1P2                           57 TIE                           
 16 GND                              58 TIE                           
 17 BCD1P3                           59 TDO                           
 18 BCD2P0                           60 GND                           
 19 BCD2P1                           61 TIE                           
 20 BCD2P2                           62 TIE                           
 21 BCD2P3                           63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 RESET0                        
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 REQ0                          
 38 VCC                              80 ADDATA0                       
 39 TIE                              81 ADDATA1                       
 40 TIE                              82 ADDATA2                       
 41 TIE                              83 ADDATA3                       
 42 GND                              84 ADDATA4                       


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : OFF
Pin Feedback                                : OFF
Input Limit                                 : 36
Pterm Limit                                 : 90
